The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that can improve electrical connection between a substrate and an upper semiconductor chip in a stack package structure.
Packaging technologies for a semiconductor device have been developed to satisfy demands for miniaturization and high capacity. One such technology is a stack package capable of satisfying requirements for miniaturization, high capacity, and mounting efficiency.
An example of the stack package includes a COC (chip-on-chip) package in which an upper semiconductor chip is stacked on a lower semiconductor chip.
In the COC package, in order to electrically connect the lower semiconductor chip with the upper semiconductor chip, circuit wiring lines such as redistribution lines or connection members such as bumps are formed.
In some cases a plurality of semiconductor chips with different sizes are stacked and electrically connected with one another on a substrate. For example, a lower semiconductor chip may be attached to a substrate and a plurality of upper semiconductor chips larger than the lower semiconductor chip may be stacked on and electrically connected with the lower semiconductor chip. However, since there is space under the periphery of the upper semiconductor chips due to overhang over the smaller lower semiconductor chip, the upper semiconductor chips are not likely to be appropriately connected with the substrate.
This may lead to degradation of the electrical characteristics and reliability of the package.